1 | Great Ideas in Computer Architecture, Intro | slides | video | |
2 | Number Representation | slides | video | P&H:2.4 Binary slides |
3 | C Intro - Basics | slides | video | K&R Ch. 1-5, C Reference Slides Brian Harvey's Intro to C |
4 | C Intro - Pointers, Arrays, Strings | slides | video | K&R:5-6 |
5 | C Memory Management | slides | video | K&R 7.8.5, 8.7 |
6 | Floating Point | slides | video | P&H:3.5, 3.9 IEEE 754 Simulator |
7 | RISC-V Intro | slides | video | P&H:2.1-2.3 |
8 | RISC-V lw, sw, Decisions I | slides | video | P&H:2.9, 2.10 , QUEST 9-10PM (only covers up to C (no floating point, no RISCV)) |
9 | RISC-V Decisions II | slides | video | P&H:2.6, 2.7, 3.2 |
10 | RISC-V Procedure | slides | video | P&H:2.8 |
11 | RISC-V Instruction Formats I | slides | video | P&H:2.5, 2.10 |
12 | RISC-V Instruction Formats II | slides | video | P&H:2.5, 2.10 |
13 | Compilation, Assembly, Linking, Loading | slides | video | P&H:2.12 |
14 | Intro to Synchronous Digital Systems | slides | video | SDS Handout |
15 | States, State Machines | slides | video | P&H:A.3-A.6 State Handout |
16 | Combinational Logic | slides | video | P&H:A.2-A.3 Logic Handout |
17 | Combinational Logic Blocks | slides | video | Blocks Handout |
18 | Single-Cycle CPU Datapath I | slides | video | P&H:4.1. 4.3 |
19 | Single-Cycle CPU Datapath II | slides | video | P&H:4.4 |
20 | Single-Cycle CPU Control | slides | video | P&H:4.4, 4.5 |
21 | Pipelining | slides | video | P&H:4.6 |
22 | Pipelining II | slides | video | P&H:4.7, 4.8 |
23 | Pipelining III | slides | video | P&H:4.10 |
24 | Caches I | slides | video | P&H:5.1, 5.2, 5.3, 5.4, 5.8, 5.9, 5.13 Cache Flowchart |
25 | Caches II | slides | video | P&H:5.1, 5.2, 5.3, 5.4, 5.8, 5.9, 5.13 Cache Flowchart |
26 | Caches III | slides | video | P&H:5.1, 5.2, 5.3, 5.4, 5.8, 5.9, 5.13 Cache Flowchart |
27 | Virtual Memory I | slides | video | P&H:5.7-5.8 |
28 | Virtual Memory II | slides | video | P&H:5.7-5.8 |
29 | Virtual Memory III | slides | video | P&H:5.7-5.8 |
30 | Flynn Taxonomy, SIMD Instructions | slides | video | P&H:1.7, 1.8, 4.10, 4.11, 6.1, 6.2, 6.3, 6.7 |
31 | Thread-Level Parallelism I | slides | video | P&H:2.11, 4.10, 5.10, 6.5 OpenMP Summary Card |
32 | Thread-Level Parallelism II | slides | video | P&H:2.11, 4.10, 5.10, 6.5 OpenMP Summary Card |
33 | Thread-Level Parallelism III | slides | video | P&H:2.11, 4.10, 5.10, 6.5 OpenMP Summary Card |
34 | MapReduce, Spark | slides | video | The Datacenter as a Computer:Ch 1, Ch 2.4, Ch 3, 5.1-5.3 |
35 | Data Centers, Cloud Computing | slides | video | The Datacenter as a Computer:Ch 1, Ch 2.4, Ch 3, 5.1-5.3 |
36 | I/O - Basics | slides | video | P&H 5.2, 5.5, 5.11, A-64 to B-66 Berkeley RAID Paper |
37 | David Patterson “A New Golden Age for Computer Architecture” | slides | video | P&H 5.2, 5.5, 5.11 |
38 | James Percy (Apple) "GPUs" | slides | video | P&H 5.2, 5.5, 5.11 |
39 | Summary and Goodbye | slides | video | |